The circuit is suitable for use in digital paging receivers which operate a battery economising regime.
1. Field of the Invention
The present invention relates to a d.c. blocking amplifier suitable for use as a stage in a limiter having a plurality of such stages. An application of such a d.c. blocking amplifier is in battery powered communications equipment such as digital paging receivers.
2. Description of the Related Art
Limiters, otherwise termed limiting amplifiers, may be used to amplify signals from low levels up to high levels suitable for driving a demodulator. Consequently they require high gains, typically 80 to 100 dB, and normally comprise a cascade of identical low gain stages. If successive low gain stages are cascaded then unless precautions are taken there is a risk of large d.c. offsets being built-up in earlier stages due to amplification which cause the later stages to be continuously hard switched in one direction and hence not amplify.
FIG. 1 of the accompanying drawings is a block schematic diagram illustrating one known technique for overcoming the problem of d.c. offsets. The drawing shows a balanced limiting amplifier comprising five low gain stages 10, 12, 14, 16 and 18 connected in cascade between inputs 19, 20 and outputs 21, 22. Such a limiting amplifier is embodied in integrated circuits Motorola MC 3362, Plessey SL 6637 and Signetics CA 3089. The signal outputs 21, 22 are fedback to respective inputs 19, 20 by respective feedback paths each including a resistor 23, 24. Two relatively large, off-chip capacitors 25, 26 are connected to the feedback paths to remove the amplified signal and thereby prevent it from feeding back to the inputs. This known circuit works satisfactorily in the sense that the d.c. offsets throughout the limiter are typically less than 1 mV. However the need for relatively large, off-chip capacitors has the disadvantages that they are not integratable and that the start-up time which is determined by the charging of the feedback capacitors will be relatively long. Modern digital pagers, such as those operating in accordance with the CCIR Radiopaging Code No. 1, normally incorporate battery economising techniques in which at least a part of the receiver is energised and de-energised in rapid succession. The time constant due to the charging of such large capacitors is greater than the economiser duty cycle which means that the limiting amplifier has to remain energised.
FIG. 2 of the accompanying drawings is a block schematic diagram illustrating another known technique for overcoming d.c. offset problems with cascaded limiting amplifiers. In this example successive gain stages 28, 30, 32, 34 and 36 are a.c. coupled by on-chip capacitors 29, 31, 33, 35 connected between successive stages. Examples of this type of limiting amplifier are the Sanyo LA 8610 and the Plessey SL 6639. When such limiting amplifiers are used in digital paging receivers, the start-up time is determined by the C-R high frequency roll-in point, typically 2 ms for a 500 Hz cut-in frequency. In the case of the Plessey SL 6639 where the resistance R is in the base circuit and is limited to about 400K ohm, then C has a value of about 800 pF for a 500 Hz high-pass filter.